onsemi MC74HC273ADWR2G Octal D-Type Flip-Flop with Clear: Datasheet, Pinout, and Application Circuit Guide

Release date:2026-11-04 Number of clicks:143

onsemi MC74HC273ADWR2G: Octal D-Type Flip-Flop with Clear

The MC74HC273ADWR2G from onsemi is a high-speed Octal D-Type Flip-Flop integrated circuit fabricated with advanced silicon-gate CMOS technology. This device is designed for a broad range of applications requiring the storage and control of data in digital systems. It features eight edge-triggered D-type flip-flops with a common buffered Clock (CP) and a common asynchronous Master Reset (MR). The MR input, when held low, clears all outputs (Q) to a low state, independent of the clock, providing immediate system control.

A key advantage of the HC logic family is its low power consumption while maintaining high speed, similar to LSTTL logic. The outputs directly interface to CMOS, NMOS, and TTL, offering significant fan-out and driving capability. The device operates over a wide voltage range of 2.0 to 6.0 V, ensuring compatibility with various system-level voltages. All inputs are protected from damage due to static discharge by diode clamps to VCC and Ground.

Pinout Configuration

The MC74HC273ADWR2G is available in a 20-pin SOIC wide-body (DW) package. The pinout is as follows:

Pins 1, 2, 3, 4, 5, 6, 7, 8: Outputs (Q0 - Q7)

Pin 9: Master Reset (MR) - Active LOW

Pin 10: Ground (GND)

Pin 11: Clock (CP) - Positive Edge-Triggered

Pins 12, 13, 14, 15, 16, 17, 18, 19: Data Inputs (D0 - D7)

Pin 20: Supply Voltage (VCC)

Application Circuit Guide

A typical application for the MC74HC273 is as an 8-bit data latch or register. In a microprocessor system, it can be used to hold the state of an address or data bus. The data inputs (D0-D7) are connected to the bus. The clock signal (CP) is driven by a decoded write pulse, latching the data present on the bus at the moment of a low-to-high clock transition. The Master Reset (MR) can be connected to a system reset line to initialize the outputs to zero on power-up or when a system reset is required.

Decoupling capacitors (e.g., 0.1 µF ceramic) should be placed as close as possible between VCC (pin 20) and GND (pin 10) to suppress high-frequency noise. Unused inputs must never be left floating and should be tied to VCC or GND through a resistor, as specified in the datasheet.

ICGOODFIND Summary:

The onsemi MC74HC273ADWR2G is a robust, high-performance octal flip-flop ideal for data storage and transfer tasks in digital designs. Its high noise immunity, low power consumption, and strong output drive make it a versatile choice for interface and buffer applications across industrial, automotive, and consumer electronics. The inclusion of a common asynchronous clear provides critical control for system initialization and management.

Keywords:

Octal D-Type Flip-Flop

Asynchronous Master Reset

Data Latch

Low Power Consumption

HC Logic Family

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